
Lixin Liu
Postdoctoral Fellow
Department of Computer Science and Engineering
The Chinese University of Hong Kong
lxliu [at] cse.cuhk.edu.hk
kerryliu1997 [at] gmail.com
[Github] | [Google Scholar] | [Linkedin]

Lixin Liu
Postdoctoral Fellow
Department of Computer Science and Engineering
lxliu [at] cse.cuhk.edu.hk
[Github] | [Google Scholar] | [Linkedin]
I am a Postdoctoral Fellow at The Chinese University of Hong Kong. I obtained my Ph.D. degree from CUHK in 2023 under the supervision of Prof. Evangeline F.Y. Young, and my B.Eng. degree from South China University of Technology in 2019. My earlier research focused on GPU-accelerated VLSI EDA. Currently, I am primarily working on LLM algorithm-system co-optimization and LLM-assisted combinatorial optimization.
ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping
Zhenxuan Xie, Lixin Liu, Tianji Liu, Evangeline F.Y. Young
International Conference On Computer Aided Design (ICCAD) 2025 (Best Paper Award Nomination)
Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration
Bangqi Fu, Lixin Liu, Martin D.F. Wong, Evangeline F.Y. Young
International Conference On Computer Aided Design (ICCAD) 2024
[Code]
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology
Lixin Liu, Tianji Liu, Bentian Jiang, Evangeline F.Y. Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2024
[Code] | [Additional Results]
Xplace: An Extremely Fast and Extensible Placement Framework
Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F.Y. Young, Martin D.F. Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2024
[Code]
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs
Bangqi Fu, Lixin Liu, Yang Sun, Wing-Ho Lau, Martin D.F. Wong, Evangeline F.Y. Young
ACM/IEEE Asia and South Pacific Design Automation Conference Technical Program (ASP-DAC) 2024 (Best Paper Award Nomination)
[Slides]
When Placement Meets GPU: GPU-Accelerated VLSI Placement and Device Placement for GPUs [Thesis]